1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming replacement gate structures with a gate electrode comprised of a deposited intermetallic compound material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, whether an NMOS or a PMOS device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by the gate electrode formed above the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration within the channel, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the appropriate control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of field effect transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, the scaling of the channel length, and associated therewith the reduction of channel resistivity and the increase of gate resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
For many early device technology generations, the gate electrode structures of most transistor elements has been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D depict one illustrative prior art method for forming an HK/MG replacement gate structure using a gate last technique. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 100 above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1A, the device 100 includes a sacrificial gate insulation layer 12, a dummy or sacrificial gate electrode 14, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 10. The various components and structures of the device 100 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 12 may be comprised of silicon dioxide, the sacrificial gate electrode 14 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 10 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 100 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings as well as various layers or regions of silicon/germanium that are typically found in high performance PMOS transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 100 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 14 (such as a protective cap layer (not shown) comprised of silicon nitride) so that at least the sacrificial gate electrode 14 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 14 and the sacrificial gate insulation layer 12 to thereby define a gate cavity 20 where a replacement gate structure will subsequently be formed. A masking layer that is typically used in such etching processes is not depicted for purposes of clarity. Typically, the sacrificial gate insulation layer 12 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 12 may not be removed in all applications.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 30 are formed in the gate cavity 20. The materials used for such replacement gate structures 30 may vary depending upon the particular application. Even in cases where the sacrificial gate insulation layer 12 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 10 within the gate cavity 20. In one illustrative example, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A, such as hafnium oxide, having a thickness of approximately 2 nm, a first metal layer 30B (e.g., a layer of titanium nitride with a thickness of about 1-2 nm), a second metal layer 30C (e.g., a layer of tantalum nitride with a thickness of about 1-2 nm) and a third metal layer 30D (e.g., a layer of titanium nitride with a thickness of about 5 nm) and a bulk metal layer 30E, such as aluminum. Ultimately, as shown in FIG. 1D, one or more CMP processes are performed to remove excess portions of the gate insulation layer 30A, the first metal layer 30B, the second metal layer 30C, the third metal layer 30D and the bulk metal layer 30E positioned outside of the gate cavity 20 to thereby define the replacement gate structure 30.
The formation of replacement gate structures is a complex process that requires highly accurate and repeatable manufacturing processes. As the gate length of transistor devices has decreased to extremely small dimensions, e.g., 10-20 nm or less, the process of forming replacement gate structures becomes even more difficult. That is, given the physical size of the gate cavity 20, and the thickness of the various layers of material that are formed to make the replacement gate structure 30, it is very difficult to form all of these layers of material in such a small gate cavity 20 and make a reliable, defect-free replacement gate structure 30.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.